In general, a digital circuit is designed to operate synchronously with a clock. That is, the digital circuit transitions to a new logic state at both the rising and falling timings of the clock or at either of the rising or falling timings of the clock. Alternatively, the digital circuit transitions to a new logic state at the rising or falling timing of the clock of each phase constituting a multiphase clock.
In the digital circuit, it is important that a duty of the clock is within an appropriate range. A duty of a single-phase clock is expressed by a ratio (tH/T) of a high level time tH to a period T. A duty of a two-phase clock is expressed by a ratio of the high level time of one of two complementary clocks constituting the two-phase clock to the period.
If the duty of the clock is out of the appropriate range, the digital circuit may not perform a desired operation. For example, in a serializer device that converts parallel data into serial data and outputs the serial data, when the duty of the clock that indicates an output timing of each bit data of the serial data significantly differs from 0.5, a so-called even/odd jitter occurs. The even/odd jitter is a state in which lengths of periods of data of odd-numbered bits and data of even-numbered bits of the output serial data are significantly different from each other. Such a jitter may cause a malfunction. Therefore, it is important that a duty of the clock is within an appropriate range.
A device for compensating for a duty of a clock is disclosed in US Patent Application Laid-Open No. 2016/0241249 (Patent Document 1), US Patent Application Laid-Open No. 2013/0063191 (Patent Document 2), and Japanese Patent Application Laid-Open No. 2012-10118 (Patent Document 3). The duty compensation device disclosed in Patent Documents 1 to 3 includes a duty adjusting unit for adjusting the duty of the clock, and a duty measuring unit for measuring information for specifying the duty of the clock. In addition, in the duty compensation device, the duty adjusting unit adjusts the duty of the clock so that the duty of the clock measured by the duty measuring unit is within an appropriate range.